The present invention relates to a semiconductor integrated circuit device, and more particularly to a technology effectively used for semiconductor integrated circuit devices such as one-chip microcomputers and system LSIs that include a plurality of functional blocks and are provided with step-down power supply circuits for lowering the voltage of external power.
Some large-scale integrated circuits are provided with two step-down circuits for operation and for standby and so constructed that during standby, the step-down circuit for operation is stopped to reduce power consumption during standby. An example of such large-scale integrated circuits is disclosed in Japanese Unexamined Patent Publication No. Hei 2(1990)-244488. Some semiconductor integrated circuit devices selectively use two different types of step-down circuits (series type and switching type) depending on the operation mode for the enhancement of power efficiency. An example of such semiconductor integrated circuit devices is disclosed in Japanese Unexamined Patent Publication No. 2001-211640.
[Patent Document 1] Japanese Unexamined Patent Publication No. Hei 2(1990)-244488
[Patent Document 2] Japanese Unexamined Patent Publication No. 2001-211640